In today electronic devices such as microprocessors, memory, and graphic processors, there is an increase in demand for higher current while reducing integrated circuit manufacturing steps. At the same time, miniaturization and high power efficiency are also important contributing factors for the successes of these integrated circuits. The conventional method of layout and manufacturing processes for switch mode voltage regulator circuits has reached their limitations and cannot meet these demands. This is because the majority of integrated circuit (IC) process uses two or more metal layers due to signal routing complexity and the delivery of high current and power.
Referring now to FIG. 1A, a schematic diagram of a switch-mode voltage regulator circuit 100A is shown that includes a controller 120, a high-side Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switch 140, and a low-side Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switch 160. Now referring to a layout scheme of FIG. 1B, a conventional layout 100B that implements switch-mode voltage regulator integrated circuit 100A is shown that includes three separate semiconductor dies connected together by bond wires. The layout of switch-mode voltage regulator integrated circuit 100A includes a controller die 120, a high side MOSFET die 140, and a low side MOSFET die 160. For handling high current and high power demands, conventional layout 100B as described above requires a manufacturing process for three different dies, each necessitating multiple metal layers. This translates directly to high manufacturing costs and performance degradation at high frequencies and high current output. In addition, at high switching frequency above 500 kHz, bond wires become parasitic and degrade the performance of switch-mode voltage regulator 100A because of the high interconnection resistance. Furthermore, the layout scheme as shown in FIG. 1B cannot meet the miniaturization requirement. Obviously because three die attachments consume large silicon area.
Accordingly, there are needs for a layout method and circuit architecture that permit fewer manufacturing steps while achieving high current and high power efficiency. At the same time, there is a need for switch mode voltage regulator integrated circuit to occupy the least amount of silicon area. The layout scheme of the present invention meets the above needs.